This invention relates to the elimination of stress between a dielectrically passivated substrate and an overlying semiconductor material. More specifically, this invention relates to the elimination of stress between a dielectrically passivated silicon wafer and a thick polycrystalline silicon layer which is deposited on the silicon wafer.
One of the main processing steps associated with dielectric isolation technology is the deposition of a thick polycrystalline silicon layer onto an oxidized surface of a silicon wafer. During this deposition, the polysilicon film tends to densify, which in turn generates a substantial residual stress between the polysilicon film and the dielectrically passivated silicon wafer. FIG. 1 illustrates the structure of the prior art which consists of a silicon substrate 10, a passivation layer 20, typically of silicon dioxide and polysilicon layer 60. In this structure, substantial residual stress is formed between layers 60 and 20.
This residual stress is harmful to final semiconductor products built from such starting materials because of the possibility that the stress can cause warping of the wafer which is one of the main causes of reduced yield during production. Additionally, microcracks and voids in device patterns, difficulties in subsequent mask alignment and degradation of the electrical parameters of semiconductor devices are all caused in part by excessive stress existing between the polysilicon film and the underlying wafer.
By reducing the ill effects of the stress thus formed it is possible to substantially improve the detrimental effects on final device yield.
It has been previously known that the significant stress which is created between a polysilicon film and the dielectrically passivated semiconductor wafer is detrimental to final device fabrication. This has been described in several publications including U. S. Davidson and F. Lee, "Dielectric-Isolated Integrated Circuit Substrate Process", Proc. IEEE, Volume 57, 1532 (1969) and T. Suzuki, et al., "Deformation in Dielectric Isolated Substrates and Its Control by a Multilayer Polysilicon Support Structure", J. Electrochem. Soc., Volume 127, 1573 (1980).
The relatively low softening temperature of a heavily doped silicon dioxide, e.g. phospho-silica glass or boro silica glass is known as was discribed in S. K. Gandhi, "VLSI Fabrication Principles" (1983), J. Wiley and Sons, Inc., Page 66. Because of the relatively low softening temperature of such glasses, the phospho-silica glass has been used in VLSI Technology to form tapered via holes. This use of phospho-silica glass is disclosed in W. Kern and R. S. Rosler, J. Vac. Sci. and Tech., Volume 14, 1082 (1977).